Show HN: Running BitNet b1.58 inside DRAM by breaking DDR4 timing rules

Category: infrastructure

Tags: bitnet, dram-computing, fpga, in-memory-computing, ai-inference

Score: 7.7/10 (Innovation: 8, Technical: 9, Documentation: 7, Utility: 6)

This project runs BitNet b1.58 neural network inference inside DRAM by intentionally violating DDR4 timing rules using a custom FPGA memory controller, leveraging well-characterized DRAM effects from academic research. It is interesting because it proposes a novel approach to overcome the memory wall by performing computation in memory without merging compute and memory silicon, though currently slow due to row-level data movement overhead.

Target audience: hardware engineers, ai researchers, systems architects

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